| HA Project Status (09/09/2011 - 18:01:57) | |||
| Project File: | HA.xise | Parser Errors: | No Errors |
| Module Name: | HA | Implementation State: | Programming File Generated |
| Target Device: | xc3s500e-4fg320 |
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| Product Version: | ISE 12.1 |
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| Design Goal: | Balanced |
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| Design Strategy: | Xilinx Default (unlocked) |
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| Environment: | System Settings |
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| Device Utilization Summary | [-] | ||||
| Logic Utilization | Used | Available | Utilization | Note(s) | |
| Number of 4 input LUTs | 2 | 9,312 | 1% | ||
| Number of occupied Slices | 1 | 4,656 | 1% | ||
| Number of Slices containing only related logic | 1 | 1 | 100% | ||
| Number of Slices containing unrelated logic | 0 | 1 | 0% | ||
| Total Number of 4 input LUTs | 2 | 9,312 | 1% | ||
| Number of bonded IOBs | 4 | 232 | 1% | ||
| Average Fanout of Non-Clock Nets | 1.50 | ||||
| Performance Summary | [-] | |||
| Final Timing Score: | 0 (Setup: 0, Hold: 0) | Pinout Data: | Pinout Report | |
| Routing Results: | All Signals Completely Routed | Clock Data: | Clock Report | |
| Timing Constraints: | ||||
| Detailed Reports | [-] | |||||
| Report Name | Status | Generated | Errors | Warnings | Infos | |
| Synthesis Report | ||||||
| Translation Report | Current | vie 9. sep 17:36:19 2011 | ||||
| Map Report | Current | vie 9. sep 17:36:22 2011 | ||||
| Place and Route Report | Current | vie 9. sep 17:36:30 2011 | ||||
| CPLD Fitter Report (Text) | ||||||
| Power Report | ||||||
| Post-PAR Static Timing Report | Current | vie 9. sep 17:36:32 2011 | ||||
| Bitgen Report | Current | vie 9. sep 17:36:37 2011 | ||||
| Secondary Reports | [-] | ||
| Report Name | Status | Generated | |
| ISIM Simulator Log | Out of Date | vie 9. sep 17:59:10 2011 | |
| WebTalk Report | Current | vie 9. sep 18:01:51 2011 | |
| WebTalk Log File | Current | vie 9. sep 18:01:57 2011 | |