ca Project Status (09/09/2011 - 20:02:06)
Project File: ca.xise Parser Errors: No Errors
Module Name: ca Implementation State: Programming File Not Generated
Target Device: xc3s500e-4fg320
  • Errors:
  
Product Version:ISE 12.1
  • Warnings:
  
Design Goal: Balanced
  • Routing Results:
  
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
  
Environment:  
  • Final Timing Score:
   
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis Report     
Translation Report     
Map Report     
Place and Route Report     
CPLD Fitter Report (Text)     
Power Report     
Post-PAR Static Timing Report     
Bitgen Report     
 
Secondary Reports [-]
Report NameStatusGenerated
WebTalk ReportCurrentvie 9. sep 20:01:58 2011
WebTalk Log FileCurrentvie 9. sep 20:02:06 2011

Date Generated: 09/09/2011 - 20:02:06