count_asc Project Status
Project File: ca.xise Parser Errors: No Errors
Module Name: count_asc Implementation State: Programming File Generated
Target Device: xc3s500e-4fg320
  • Errors:
No Errors
Product Version:ISE 12.1
  • Warnings:
1 Warning (1 new)
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
All Constraints Met
Environment: System Settings
  • Final Timing Score:
0  (Timing Report)
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Flip Flops 29 9,312 1%  
Number of 4 input LUTs 4 9,312 1%  
Number of occupied Slices 16 4,656 1%  
    Number of Slices containing only related logic 16 16 100%  
    Number of Slices containing unrelated logic 0 16 0%  
Total Number of 4 input LUTs 28 9,312 1%  
    Number used as logic 4      
    Number used as a route-thru 24      
Number of bonded IOBs 5 232 2%  
Number of BUFGMUXs 1 24 4%  
Average Fanout of Non-Clock Nets 1.25      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentvie 9. sep 19:57:13 2011001 Info (1 new)
Translation ReportCurrentvie 9. sep 20:01:34 2011000
Map ReportCurrentvie 9. sep 20:01:37 2011002 Infos (0 new)
Place and Route ReportCurrentvie 9. sep 20:01:51 201101 Warning (1 new)4 Infos (0 new)
Power Report     
Post-PAR Static Timing ReportCurrentvie 9. sep 20:01:53 2011005 Infos (0 new)
Bitgen ReportCurrentvie 9. sep 20:01:58 2011000
 
Secondary Reports [-]
Report NameStatusGenerated
WebTalk ReportCurrentvie 9. sep 20:01:58 2011
WebTalk Log FileCurrentvie 9. sep 20:02:06 2011

Date Generated: 09/09/2011 - 21:09:00