Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
 
 
Software Version and Target Device
Product Version: ISE:12.1 (WebPack) - M.53d Target Family: Spartan3E
OS Platform: NT64 Target Device: xc3s500e
Project ID (random number) 4b904a2f349849d9ac7e42ae21e52822.6F2DFB8EEE294249B54B95ED39FD7327.2 Target Package: fg320
Registration ID __0_0_0 Target Speed: -4
Date Generated 2011-09-09T20:01:58 Tool Flow ISE
 
User Environment
OS Name Microsoft OS Release Service Pack 1 (build 7601)
CPU Name Intel(R) Core(TM) i7 CPU 920 @ 2.67GHz CPU Speed 2660 MHz
 
Device Usage Statistics
Macro StatisticsMiscellaneous StatisticsNet StatisticsSite Usage
Counters=2
  • 25-bit up counter=1
  • 4-bit up counter=1
 		MiscellaneousStatistics
  • AGG_BONDED_IO=5
  • AGG_IO=5
  • AGG_SLICE=16
  • NUM_4_INPUT_LUT=28
  • NUM_BONDED_IBUF=1
  • NUM_BONDED_IOB=4
  • NUM_BUFGMUX=1
  • NUM_CYMUX=24
  • NUM_LUT_RT=24
  • NUM_SLICEL=16
  • NUM_SLICE_FF=29
  • NUM_XOR=25
 		NetStatistics
  • NumNets_Active=48
  • NumNets_Gnd=1
  • NumNets_Vcc=1
  • NumNodesOfType_Active_CLKPIN=16
  • NumNodesOfType_Active_CNTRLPIN=1
  • NumNodesOfType_Active_DOUBLE=13
  • NumNodesOfType_Active_DUMMY=35
  • NumNodesOfType_Active_DUMMYESC=1
  • NumNodesOfType_Active_GLOBAL=8
  • NumNodesOfType_Active_INPUT=51
  • NumNodesOfType_Active_IOBOUTPUT=1
  • NumNodesOfType_Active_OMUX=36
  • NumNodesOfType_Active_OUTPUT=42
  • NumNodesOfType_Active_PREBXBY=2
  • NumNodesOfType_Active_VFULLHEX=2
  • NumNodesOfType_Vcc_CNTRLPIN=1
  • NumNodesOfType_Vcc_INPUT=1
  • NumNodesOfType_Vcc_PREBXBY=1
  • NumNodesOfType_Vcc_VCCOUT=2
 SiteStatistics
  • IBUF-DIFFMI=1
  • IOB-DIFFM=2
  • IOB-DIFFS=2
  • SLICEL-SLICEM=2
 		SiteSummary
  • BUFGMUX=1
  • BUFGMUX_GCLKMUX=1
  • BUFGMUX_GCLK_BUFFER=1
  • IBUF=1
  • IBUF_INBUF=1
  • IBUF_PAD=1
  • IOB=4
  • IOB_OUTBUF=4
  • IOB_PAD=4
  • SLICEL=16
  • SLICEL_C1VDD=1
  • SLICEL_CYMUXF=12
  • SLICEL_CYMUXG=12
  • SLICEL_F=14
  • SLICEL_FFX=14
  • SLICEL_FFY=15
  • SLICEL_G=14
  • SLICEL_GNDF=11
  • SLICEL_GNDG=12
  • SLICEL_XORF=13
  • SLICEL_XORG=12
 
Configuration Data
BUFGMUX
  • S=[S_INV:1] [S:0]
 BUFGMUX_GCLKMUX
  • DISABLE_ATTR=[LOW:1]
  • S=[S_INV:1] [S:0]
 IBUF_PAD
  • IOATTRBOX=[LVCMOS25:1]
 IOB
  • O1=[O1_INV:0] [O1:4]
 IOB_OUTBUF
  • IN=[IN_INV:0] [IN:4]
 IOB_PAD
  • DRIVEATTRBOX=[12:4]
  • IOATTRBOX=[LVCMOS25:4]
  • SLEW=[SLOW:4]
 SLICEL
  • BX=[BX_INV:0] [BX:1]
  • BY=[BY:1] [BY_INV:0]
  • CIN=[CIN_INV:0] [CIN:12]
  • CLK=[CLK:16] [CLK_INV:0]
  • SR=[SR:1] [SR_INV:0]
 SLICEL_CYMUXF
  • 0=[0:12] [0_INV:0]
  • 1=[1_INV:0] [1:12]
 SLICEL_CYMUXG
  • 0=[0:12] [0_INV:0]
 SLICEL_FFX
  • CK=[CK:14] [CK_INV:0]
  • D=[D:14] [D_INV:0]
  • FFX_INIT_ATTR=[INIT0:14]
  • FFX_SR_ATTR=[SRLOW:14]
  • LATCH_OR_FF=[FF:14]
  • SYNC_ATTR=[ASYNC:14]
 SLICEL_FFY
  • CK=[CK:15] [CK_INV:0]
  • D=[D:15] [D_INV:0]
  • FFY_INIT_ATTR=[INIT0:15]
  • FFY_SR_ATTR=[SRLOW:15]
  • LATCH_OR_FF=[FF:15]
  • SR=[SR:1] [SR_INV:0]
  • SYNC_ATTR=[ASYNC:14] [SYNC:1]
 SLICEL_XORF
  • 1=[1_INV:0] [1:13]
 
Pin Data
BUFGMUX
  • I0=1
  • O=1
  • S=1
 BUFGMUX_GCLKMUX
  • I0=1
  • OUT=1
  • S=1
 BUFGMUX_GCLK_BUFFER
  • IN=1
  • OUT=1
 IBUF
  • I=1
  • PAD=1
 IBUF_INBUF
  • IN=1
  • OUT=1
 IBUF_PAD
  • PAD=1
 IOB
  • O1=4
  • PAD=4
 IOB_OUTBUF
  • IN=4
  • OUT=4
 IOB_PAD
  • PAD=4
 SLICEL
  • BX=1
  • BY=1
  • CIN=12
  • CLK=16
  • COUT=12
  • F1=14
  • F2=1
  • F3=1
  • F4=1
  • G1=14
  • G2=2
  • G3=1
  • SR=1
  • XQ=14
  • YQ=15
 SLICEL_C1VDD
  • 1=1
 SLICEL_CYMUXF
  • 0=12
  • 1=12
  • OUT=12
  • S0=12
 SLICEL_CYMUXG
  • 0=12
  • 1=12
  • OUT=12
  • S0=12
 SLICEL_F
  • A1=14
  • A2=1
  • A3=1
  • A4=1
  • D=14
 SLICEL_FFX
  • CK=14
  • D=14
  • Q=14
 SLICEL_FFY
  • CK=15
  • D=15
  • Q=15
  • SR=1
 SLICEL_G
  • A1=14
  • A2=2
  • A3=1
  • D=14
 SLICEL_GNDF
  • 0=11
 SLICEL_GNDG
  • 0=12
 SLICEL_XORF
  • 0=13
  • 1=13
  • O=13
 SLICEL_XORG
  • 0=12
  • 1=12
  • O=12
 
Tool Usage
Command Line History
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -i -p xc3s500e-fg320-4 <ise_file> <fname>.ngd
  • map -intstyle ise -p xc3s500e-fg320-4 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s500e-fg320-4 <ise_file> <fname>.ngd
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s500e-fg320-4 <ise_file> <fname>.ngd
  • map -intstyle ise -p xc3s500e-fg320-4 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
 
Software Quality
Run Statistics
bitgen 5 5 0 0 0 0 0
map 5 5 0 0 0 0 0
ngdbuild 6 6 0 0 0 0 0
par 5 5 0 0 0 0 0
trce 5 5 0 0 0 0 0
xps 1 1 0 0 0 0 0
xst 10 10 0 0 0 0 0
 
Help Statistics
Help files
/doc/usenglish/isehelp/ism_db_clock.htm ( 1 ) /doc/usenglish/isehelp/pn_db_nsw_select_source_type.htm ( 1 )
 
Project Statistics
PROP_Enable_Message_Filtering=false PROP_FitterReportFormat=HTML
PROP_LastAppliedGoal=Balanced PROP_LastAppliedStrategy=Xilinx Default (unlocked)
PROP_ManualCompileOrderImp=false PROP_PropSpecInProjFile=Store all values
PROP_Simulator=ISim (VHDL/Verilog) PROP_SynthTopFile=changed
PROP_Top_Level_Module_Type=HDL PROP_UseSmartGuide=false
PROP_UserConstraintEditorPreference=Text Editor PROP_intProjectCreationTimestamp=2011-09-09T19:48:17
PROP_intWbtProjectID=6F2DFB8EEE294249B54B95ED39FD7327 PROP_intWbtProjectIteration=2
PROP_intWorkingDirLocWRTProjDir=Same PROP_intWorkingDirUsed=No
PROP_lockPinsUcfFile=changed PROP_AutoTop=true
PROP_DevFamily=Spartan3E PROP_DevDevice=xc3s500e
PROP_DevFamilyPMName=spartan3e PROP_DevPackage=fg320
PROP_Synthesis_Tool=XST (VHDL/Verilog) PROP_DevSpeed=-4
PROP_PreferredLanguage=VHDL FILE_UCF=1
FILE_VHDL=1
 
Unisim Statistics
NGDBUILD_PRE_UNISIM_SUMMARY
NGDBUILD_NUM_BUFGP=1 NGDBUILD_NUM_FD=28 NGDBUILD_NUM_FDR=1 NGDBUILD_NUM_GND=1
NGDBUILD_NUM_INV=1 NGDBUILD_NUM_LUT1=24 NGDBUILD_NUM_LUT2=1 NGDBUILD_NUM_LUT3=1
NGDBUILD_NUM_LUT4=1 NGDBUILD_NUM_MUXCY=24 NGDBUILD_NUM_OBUF=4 NGDBUILD_NUM_VCC=1
NGDBUILD_NUM_XORCY=25
NGDBUILD_POST_UNISIM_SUMMARY
NGDBUILD_NUM_BUFG=1 NGDBUILD_NUM_FD=28 NGDBUILD_NUM_FDR=1 NGDBUILD_NUM_GND=1
NGDBUILD_NUM_IBUFG=1 NGDBUILD_NUM_INV=1 NGDBUILD_NUM_LUT1=24 NGDBUILD_NUM_LUT2=1
NGDBUILD_NUM_LUT3=1 NGDBUILD_NUM_LUT4=1 NGDBUILD_NUM_MUXCY=24 NGDBUILD_NUM_OBUF=4
NGDBUILD_NUM_VCC=1 NGDBUILD_NUM_XORCY=25